Temperature-compensated semiconductor resistor and semiconductor integrated circuit having the semiconductor resistor

ABSTRACT

A temperature-compensated semiconductor resistor includes two series-connected semiconductor resistance elements having mutually inverse resistive temperature-dependent responses in a temperature range of interest. The semiconductor resistance elements are preferably made of doped polycrystalline semiconductor material such as polycrystalline silicon that is oppositely doped, i.e. n-doped and p-doped, respectively. A semiconductor integrated circuit, in particular a CMOS circuit, containing a semiconductor resistor, is also provided.

BACKGROUND OF THE INVENTION

[0001] Field of the Invention

[0002] The invention relates to a temperature-compensated semiconductor resistor. In particular, the invention relates to a semiconductor resistor which varies little with temperature in a temperature range of interest. In addition, the invention relates to a semiconductor integrated circuit in which such a semiconductor resistor is provided.

[0003] Electrical resistances can appear in various forms intentionally or unintentionally in semiconductor integrated circuits. In their unwanted form they constitute parasitic circuit elements having properties which must be estimated so that their negative effects can be minimized and countermeasures taken. If, however, semiconductor resistances are required for an electronic function, one must know their dimensions and electrical properties very precisely.

[0004] The classic form of a resistor integrated in a semiconductor circuit is a well resistor, i.e. a diffused or implanted p-region in a surrounding n-region. In standard CMOS circuits, such resistors are usually made of polycrystalline silicon with various characteristics. However, the disadvantage of typical CMOS resistors is that their resistance is highly temperature-dependent in the usual ambient temperature range. That can have detrimental effects on the performance of the semiconductor component, or lead to complete failure of the component.

SUMMARY OF THE INVENTION

[0005] It is accordingly an object of the invention to provide a temperature-compensated semiconductor resistor and a semiconductor integrated circuit having the semiconductor resistor, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which have an improved temperature response, in particular with a reduced temperature dependence in a temperature range of interest.

[0006] With the foregoing and other objects in view there is provided, in accordance with the invention, a temperature-compensated semiconductor resistor, comprising two series-connected semiconductor resistance elements having mutually inverse resistive temperature responses or temperature-dependent resistance courses, in a temperature range of interest that is the normal ambient temperature during operation of the associated semiconductor circuit. Thus, within this range, one of the two resistance elements should have a positive temperature coefficient i.e. an electrical resistance that increases as the temperature rises, and the other one should have a negative temperature coefficient, i.e. an electrical resistance that decreases as the temperature rises.

[0007] A first connecting contact is disposed at one end of the semiconductor resistor, that is to say on the first of the two semiconductor resistance elements. The other connecting contact is located at the other end of the semiconductor resistor, that is to say on the second of the two semiconductor resistance elements. This results in a series circuit including the semiconductor resistance elements, and the total resistance of the semiconductor resistor equals the sum of the resistances of the two semiconductor resistance elements. The inverse resistive temperature responses of each of the resistance elements with respect to each other provide mutual compensation, so that the process of addition means that the resistive temperature characteristic of the semiconductor resistor is relatively flat.

[0008] In accordance with another feature of the invention, the semiconductor resistance elements are made of oppositely doped polycrystalline semiconductor material, in particular polycrystalline silicon. In crystalline silicon, the conductivity with respect to the temperature is determined by the decreasing mobility of the charge carriers with increasing temperature. However, in polycrystalline silicon, the charge transport mechanisms across the grain boundaries must be taken into account. One can thus obtain a negative or positive temperature coefficient depending on the charge state of the crystal defects making up a grain boundary. In experiments, one observes in p-doped, particularly p⁺-doped, polycrystalline silicon a resistance that increases with rising temperature, while in n-doped, particularly n⁺-doped, polycrystalline silicon a resistance that falls with rising temperature is observed. In the semiconductor resistor according to the invention, one can select different doping concentrations for hi the oppositely doped semiconductor resistance elements.

[0009] In accordance with a concomitant feature of the invention, if the semiconductor resistance elements are formed from n-doped and p-doped semiconductor regions, they are physically separated by a high-conductivity connecting layer. The connecting layer provides a low resistance electrical connection between the two semiconductor resistance elements. The connecting layer may be a metallic layer or possibly even a very highly doped semiconductor layer. However, the n-doped and p-doped semiconductor regions must not be directly adjacent, since that would create an unwanted p-n junction.

[0010] Other features which are considered as characteristic for the invention are set forth in the appended claims.

[0011] Although the invention is illustrated and described herein as embodied in a temperature-compensated semiconductor resistor and a semiconductor integrated circuit having the semiconductor resistor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

[0012] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a diagrammatic, plan view of one embodiment of a semiconductor resistor according to the invention;

[0014]FIGS. 2A and 2B are graphs of temperature-dependent resistance curves for the semiconductor resistance elements; and

[0015]FIG. 3 is a graph of a temperature-dependent resistance curve for the semiconductor resistor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Referring now to the figures of the drawings in detail and first, particularly, to FIG. 1 thereof, there is seen a layout of a semiconductor resistor 10 according to the invention, which has two resistance elements 1 and 2 that are connected in series and made of oppositely doped polycrystalline substrates, in this case a relatively highly n-doped, i.e. n⁺-doped resistance element 1, and a relatively highly p-doped, i.e. p⁺-doped resistance element 2. A highly conductive connecting layer 3, for instance made of metal, lies between the resistance elements 1 and 2. Suitable contact layers, such as semiconductor alloy layers, may also be applied to interfaces between the resistance elements 1 and 2 and the metallic connecting layer 3. The resistance elements 1 and 2 must not be directly adjacent, since that would create a p-n junction. Suitable high-conductivity contact layers 1 a and 2 a are applied to side ends of the semiconductor resistor 10. External connections to the semiconductor resistor 10 can be made through the use of the contact layers 1 a and 2 a.

[0017] In an integrated CMOS circuit, the resistance elements 1 and 2 can be formed from suitably highly doped polysilicon layers embedded in a suitable way in the topography of the CMOS circuit and contacted at their (side) ends, as shown.

[0018] The semiconductor resistor 10 has a defined constant layer thickness (at right angles to the plane of the drawing) and a defined constant width W. Its overall length L is divided into lengths L_(n) and L_(p) of its resistance elements 1 and 2, so that L=L_(n)+L_(p). The parameters L, L_(n) and L_(p) are set in such a way that, for given temperature-dependent specific resistances:

[0019] on one hand, one obtains a defined resistance R_(TCOMP) (T_(COMP)) for the semiconductor resistor 10 at a specific ambient temperature T_(COMP); and

[0020] on the other hand, the temperature dependence of the resistance at this temperature is a minimum. Mathematically, this means that the first derivative of R(T) at the point T_(COMP) should equal zero.

[0021] As a geometrical and computational aid to determining L, L_(n) and L_(p), the resistance elements 1 and 2 are first divided into square base areas SQ_(n) and SQ_(p), having a length which therefore equals the width W of the semiconductor resistor 10. Such a base area is also given the arbitrary unit of 1 square. At the end of the calculation, the lengths L_(n) and L_(p) are each given as multiples of the lengths of SQ_(n) and SQ_(p), that is to say effectively of W. Thus, one obtains L_(n)=S_(n)×W and L_(p)=S_(p)×W, where the numbers S_(n) and S_(p) give the ratio of the length/width of each resistance element, respectively. The numbers S_(n) and S_(p) are real positive numbers and need not be integers.

[0022] Next, one considers the temperature-dependent resistance of one square of the n⁺-doped and the p⁺-doped polysilicon, in respectively. The corresponding curves are shown in FIGS. 2A and 2B. One can clearly see the negative gradient of the n-doped polyresistance in contrast to the slightly positive gradient of the p-doped polyresistance.

[0023] These curves can be represented as a series truncated to the second term as shown below in equation (1). The first derivative with respect to the temperature is then obtained from this in equation (2).

r(T)=r(T ₀)·[1+T _(C1)·(T−T ₀)+T _(C2)·(T−T ₀)²]in Ω  (1)

δr(T)/δT=r(T ₀)·[T _(C1)+2·T _(C2)·(T−T ₀)]in Ω/° C.  (2)

[0024] where T_(C1), T_(C2) and r(T₀) are values governed by the technology.

[0025] Since the two resistance elements 1 and 2 are connected in series, the following equation holds for the dependence of the total resistance R on the temperature:

R _(TCOMP)(T)=R^(n+)(T)+R ^(p+)(T)=S _(n) r ^(n+)(T)+S _(p) r ^(p+)(T)  (3)

[0026] Differentiating equation (3) with respect to T, assuming there is a local optimum, i.e. a zero point of the first derivative, one obtains the following for the temperature T_(COMP):

δR _(TCOMP)(T=T _(COMP))/δT=S _(n) ·δr ^(n+)(T)/δT+S _(p) ·δr ^(p+() T)/δT=0  (4)

[0027] Therefore, and applying equation (2), the resistance ratio is defined as: $\begin{matrix} {K = {{R^{n +}/R^{p +}} = {{S_{n}/S_{p}} = \left\{ {{- {r^{p +}\left( T_{0} \right)}} \cdot {\left\lbrack {T_{C1}^{p +} + {2 \cdot T_{C2}^{p +} \cdot \left( {T_{COMP} - T_{0}} \right)}} \right\rbrack/\left\{ {{r^{n +}\left( T_{0} \right)} \cdot \left\lbrack {T_{C1}^{n +} + {2 \cdot T_{C2}^{n +} \cdot \left( {T_{COMP} - T_{0}} \right)}} \right\rbrack} \right\}}} \right.}}} & (5) \end{matrix}$

[0028] From which one can obtain the resistances:

R ^(p+)=1/(1+k)·R _(TCOMP) and R ^(n+) =k(1+k)·R _(TCOMP)  (6)

[0029] In the following exemplary embodiment, the resistance curves shown in FIGS. 2A and 2B are assumed for one square of the resistance elements 1 and 2, respectively. The following parameter values apply to these curves: Units n⁺ poly-Si p⁺ poly-Si R(T₀) Ω 340 175 T_(C1) 1/° C.  −1.55 × 10⁻³  2.75 × 10⁻⁴ T_(C2) 1/° C.²  2.827 × 10⁻⁶  9.9 × 10⁻⁷

[0030] Using these resistance elements one should obtain a resistance R_(COMP) (T_(COMP))=100,000 Ω, T_(COMP)=50° C. and T₀=27° C.

[0031] Applying equations (5) and (6) under these assumptions yields k=0.116 and length/width ratios for the resistance elements of S_(n)=54 and S_(p)=466. The surface areas of the resistance elements are thus given by R_(sq) ^(p)=466 squares and R_(sq) ^(n)=54 squares.

[0032] The temperature response of the total resistance R is shown in FIG. 3. One can see the local minimum at R=100,000Ω.

[0033] The object according to the invention of creating a resistor that at a given temperature has a defined resistance which should have minimum variation with changes in the ambient temperature, is thus achieved. 

I claim:
 1. A temperature-compensated semiconductor resistor, comprising: two series-connected semiconductor resistance elements having mutually inverse resistive temperature responses in a temperature range of interest.
 2. The semiconductor resistor according to claim 1, wherein said semiconductor resistance elements contain doped polycrystalline semiconductor material of opposite conductivity types.
 3. The semiconductor resistor according to claim 2, wherein said semiconductor material is polycrystalline silicon.
 4. The semiconductor resistor according to claim 1, including an electrically conductive connecting layer disposed between said semiconductor resistance elements.
 5. The semiconductor resistor according to claim 4, wherein said electrically conductive connecting layer is made of metal.
 6. The semiconductor resistor according to claim 1, including: a defined semiconductor resistor width and a defined semiconductor resistor depth; said resistance elements together having an overall length L; said resistance elements having widths, being disposed adjacent each other along said widths and having sub-lengths L_(n), L_(p); and said overall length L and said sub-lengths L_(n), L_(p) explicitly determined by: a temperature-dependent resistance R(T) having a specified value at a defined temperature T_(COMP); and the first derivative of the temperature-dependent resistance R(T) with respect to temperature dR/dT being equal to 0 at the defined temperature T_(COMP).
 7. A semiconductor integrated circuit, comprising: a temperature-compensated semiconductor resistor including two series-connected semiconductor resistance elements having mutually inverse resistive temperature responses in a temperature range of interest.
 8. A CMOS circuit, comprising: a temperature-compensated semiconductor resistor including two series-connected semiconductor resistance elements having mutually inverse resistive temperature responses in a temperature range of interest. 